A critical part of any advanced semiconductor integrated circuit involves the one or more metallization levels used to contact and interconnect the active semiconductor areas, themselves usually residing in a fairly well defined crystalline silicon substrate. Although it is possible to interconnect a few transistors or other semiconductor devices, such as memory capacitors, within or immediately on top of the semiconductor level, the increasingly complex topology of multiply connected devices soon necessitates another level of interconnect. Typically, an active silicon layer with transistors and capacitors formed therein is overlaid with a dielectric layer, for example, silicon dioxide. Contact holes are etched through the dielectric layer to particular contacting areas of the silicon devices. A metal is filled into the contact holes and is also deposited on top of the dielectric layer to form horizontal interconnects between the silicon contacts and other electrical points. Such a process is referred to as metallization.
A single level of metallization may suffice for simple integrated circuits of small capacity. However, dense memory chips and especially complex logic devices require additional levels of metallization since a single level does not provide the required level of interconnection between active areas. Additional metallization levels are achieved by depositing over the previous metallized horizontal interconnects another level of dielectric and repeating the process of etching holes, now called vias, through the dielectric, filling the vias and overlaying the added dielectric layer with a metal, and defining the metal above the added dielectric as an additional wiring layer. Very advanced logic device, for example, fifth-generation microprocessors, may have five or more levels of metallization.
Conventionally, the metallized layers have been composed of aluminum and aluminum-based alloys additionally comprising at most a few percent of alloying elements such as copper and silicon. The metallization deposition has typically been accomplished by physical vapor deposition (PVD), also known as sputtering. A conventional PVD reactor 10 is illustrated schematically in cross section in FIG. 1, and the illustration is based upon the Endura PVD Reactor available from Applied Materials, Inc. of Santa Clara, Calif. The reactor 10 includes a vacuum chamber 12 sealed to a PVD target 14 of the material to be sputter deposited on a wafer 16 held on a heater pedestal 18. A shield 20 held within the chamber protects the chamber wall 12 from the sputtered material and provides the anode grounding plane. A selectable DC power supply 22 biases the target negatively to about -600VDC with respect to the shield 20. Conventionally, the pedestal 18 and hence the wafer is left electrically floating. The heater pedestal 18 includes a resistive heater 24 powered by an adjustable electrical power supply 26.
A gas source 28 of sputtering working gas, typically chemically inactive argon, supplies the argon to the chamber through a mass flow controller 30. A vacuum pump system 32 maintains the chamber at a low pressure. Although the base pressure can be in the range of about 10.sup.-7 to 10.sup.-8 Torr, the argon pressure is kept between 1 and 100 mTorr. A computer-based controller 34 controls the operation of the parts of the reactor including the DC power supply 22, the heater power supply 26, and the mass flow controller 30.
When the argon is admitted into the chamber, the DC voltage ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 14. The ions strike the target 14 at a substantial energy and cause target atoms or atom clusters to be sputtered from the target 14. Some of the target particles strike the wafer 16 and are thereby deposited on it.
To provide efficient sputtering, a magnetron 36 is positioned in back of the target. It has opposed magnets 38, 40 creating a magnetic field within the chamber in the neighborhood of the magnets 38, 40. The magnetic field traps electrons, and for charge neutrality, the ion density also increases to form a high-density plasma region 42 within the chamber adjacent to the magnetron 36. The high-density plasma increases the sputtering rate, and the magnetron 36 is scanned over the back of the target 14 to provide a more uniform sputtering process.
With the continuing miniaturization of integrated circuits, the demands upon the metallization have increased. Many now believe that aluminum metallization should be replaced by copper metallization. Murarka et al. provide a comprehensive review article on copper metallization in "Copper metallization for ULSI and beyond," Critical Reviews in Solid State and Materials Science, vol. 10, no. 2, 1995, pp. 87-124 . Copper offers a number of advantages. Its bulk resistivity is considerably less than that of aluminum, 1.67 .mu..OMEGA.-cm vs. 2.7 .mu..OMEGA.-cm for pure material, and any reduction in resistivity offers significant advantages as the widths and thicknesses of the metallization interconnects continue to decrease. Furthermore, a continuing problem with aluminum metallization is the tendency of aluminum atoms in an aluminum metal to migrate along the metallization interconnects under high current densities, especially migrating away from hot spots, in a process called electromigration. Any excessive amount of such migration will break an aluminum interconnect and render inoperable the integrated circuit. Copper-based alloys exhibit significantly reduced levels of electromigration over aluminum and its alloys.
Thus, in many ways, the bulk behavior of copper is superior to that of aluminum, but two major problems have impeded its adoption in commercial circuits.
It has proven difficult to etch copper by a dry etch process, that is, by plasma etching. The etch problem seems to have been circumvented by the development of the damascene process in which a trench, perhaps with a via hole at its bottom, is etched into the silicon dioxide dielectric layer. The trench follows the intended path of the horizontal interconnect. A blanket deposition of copper fills the trench and additionally forms a layer over the dielectric. The wafer is then subjected to chemical mechanical polishing (CMP) to remove all copper exposed above the top of the trench and thus to leave a copper interconnect in the trench.
Another set of problems addressed by this invention involves the interfaces between the copper and other parts of the integrated circuit. A principal advantage of aluminum is its good interfacial characteristics. Aluminum forms a stable oxide layer, Al.sub.2 O.sub.3, and it forms strong chemical bonds with silicon. Copper oxidizes, but the oxide is not stable and continues to grow over time upon exposure to a moist oxygen ambient. Copper and copper oxides do not adhere well to silicon dioxide. Finally, copper diffuses very quickly through silicon dioxide and can produce a short through or across the dielectric layer unless means are adopted to prevent the copper from entering the silicon dioxide. In the prior art, a separate barrier layer was deposited over the silicon dioxide before the copper was deposited to prevent the copper from diffusing into and through the oxide.
Murarka et al. in the aforecited review article recommend alloying copper with magnesium or aluminum to improve the interfacial qualities. Later work done by the Murarka group at Rensselaer Polytechnic Institute and their collaborators have developed a useful technique for forming dependable copper interconnects and provide a model for its operation. As Lanford et al. describe in "Low-temperature passivation of copper by doping with Al or Mg," Thin Solid Films, vol. 262, 1995, pp. 234-241, sputtering is used, as illustrated in the schematic cross section of FIG. 2, to deposit a film 44 of copper alloy on a substrate 46. Examples of the alloying element include aluminum and magnesium. The copper alloy film 44 can be deposited as alternating layers of copper and the alloying element, or the two constituents can be co-sputtered, for example, by use of a copper alloy sputtering target. After completion of the sputtering at near to room temperature, the wafer is annealed, for example, at 400.degree. C. in argon for 30 minutes. As illustrated in the cross section of FIG. 3 the annealing causes a large fraction of the magnesium to diffuse to the outside of a remaining copper film 48 and to react with any oxygen present at the interfaces to form a film 49 of magnesium oxide. The MgO film 49 encapsulates the Mg-alloyed Cu body 44. The upper free surface of the copper film 48 is passivated by the MgO film 49 Magnesium oxide is a stable oxide and stops growing at a thickness in the range of 5 to 7 nm. The thin oxide is not believed to cause a high contact resistance, but in any case the oxide can be removed by a sputter etch prior to the deposition of a subsequent metallization. Lanford et al., ibid., suggest that the free surface is oxidized to MgO by oxygen impurities in the argon.